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Multiple slave-devices are supported through selection with individual slave select SS , sometimes called chip select CS , lines. Sometimes SPI is called a four-wire serial bus, contrasting with three- , two- , and one-wire serial buses.

The SPI may be accurately described as a synchronous serial interface, [1] but it is different from the Synchronous Serial Interface SSI protocol, which is also a four-wire synchronous serial communication protocol.

The SSI protocol employs differential signaling and provides only a single simplex communication channel. SPI is one master and multi slave communication.

Slave Select has the same functionality as chip select and is used instead of an addressing concept. The signal names above can be used to label both the master and slave device pins as well as the signal lines between them in an unambiguous way, and are the most common in modern products.

Pin names are always capitalized e. If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require a falling edge of the chip select signal to initiate an action.

With multiple slave devices, an independent SS signal is required from the master for each slave device. Most slave devices have tri-state outputs so their MISO signal becomes high impedance electrically disconnected when the device is not selected.

Devices without tri-state outputs cannot share SPI bus segments with other devices without using an external tri-state buffer.

To begin communication, the bus master configures the clock, using a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line.

If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.

During each SPI clock cycle, a full-duplex data transmission occurs. This sequence is maintained even when only one-directional data transfer is intended.

Transmissions normally involve two shift registers of some given word-size, such as eight bits, one in the master and one in the slave; they are connected in a virtual ring topology.

Data is usually shifted out with the most significant bit first. On the clock edge, both master and slave shift out a bit and output it on the transmission line to the counterpart.

On the next clock edge, at each receiver the bit is sampled from the transmission line and set as a new least-significant bit of the shift register.

After the register bits have been shifted out and in, the master and slave have exchanged register values.

If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles.

When complete, the master stops toggling the clock signal, and typically deselects the slave. Transmissions often consist of eight-bit words.

However, other word-sizes are also common, for example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC by Texas Instruments , or twelve-bit words for many digital-to-analog or analog-to-digital converters.

In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data.

The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device.

SPI master and slave devices may well sample data at different points in that half cycle. The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention, with CPOL as the high order bit and CPHA as the low order bit:.

Note that in Full Duplex operation, the Master device could transmit and receive with different modes. For instance, it could transmit in Mode 0 and be receiving in Mode 1 at the same time.

In the independent slave configuration, there is an independent chip select line for each slave. This is the way SPI is normally used.

The master asserts only one chip select at a time. Pull-up resistors between power source and chip select lines are recommended for systems where the master's chip select pins may default to an undefined state.

Since the MISO pins of the slaves are connected together, they are required to be tri-state pins high, low or high-impedance , where the high-impedance output must be applied when the slave is not selected.

Slave devices not supporting tri-state may be used in independent slave configuration by adding a tri-state buffer chip controlled by the chip select signal.

Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc.

The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses.

The whole chain acts as a communication shift register ; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI.

Each slave copies input to output in the next clock cycle until active low SS line goes high. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave.

Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified.

Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access the scan chain of a digital IC by issuing a command word of one size perhaps 32 bits and then getting a response of a different size perhaps bits, one for each pin in that scan chain.

Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real time clock chips, SDIO , [6] and headset jack insertions from the sound codec in a cell phone.

Interrupts are not covered by the SPI standard; their usage is neither forbidden nor specified by the standard. In other words, interrupts are outside the scope of the SPI standard and are optionally implemented independently from it.

The example is written in the C programming language. The chip select line must be activated, which normally means being toggled low, for the peripheral before the start of the transfer, and then deactivated afterward.

Most peripherals allow or require several transfers while the select line is low; this routine might be called several times before deselecting the chip.

These chips usually include SPI controllers capable of running in either master or slave mode. Chip or FPGA based designs sometimes use SPI to communicate between internal components; on-chip real estate can be as costly as its on-board cousin.

While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles.

Consequently, the JTAG interface is not intended to support extremely high data rates. The SPI bus is a de facto standard. However, the lack of a formal standard is reflected in a wide variety of protocol options.

Different word sizes are common. Every device defines its own protocol, including whether it supports commands at all.

Some devices are transmit-only; others are receive-only. Chip selects are sometimes active-high rather than active-low.

Some protocols send the least significant bit first. Sending data from slave to master may use the opposite clock edge as master to slave.

Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device.

Many of the read clocks run from the chip select line. Some devices require an additional flow control signal from slave to master, indicating when data is ready.

This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words.

Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time.

Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response.

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